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HT82B40R/HT82B40A I/O MCU with USB Interface
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * Integrated 1.5kW resistor between V33O and
fSYS=6M/12MHz: 3.3V~5.5V
* Low voltage reset function * 34 bidirectional I/O lines (max.) * 8-bit programmable timer/event counter with
D- pins for USB applications
* Fully integrated 6MHz or 12MHz oscillator * All I/O pins have wake-up functions * Power-down function and wake-up feature reduce
overflow interrupt
* 16-bit programmable timer/event counter and
power consumption
* 8-level subroutine nesting * Up to 0.33ms instruction cycle with 12MHz system
overflow interrupts
* Watchdog Timer * PS2 and USB modes supported * USB 2.0 low speed function * 3 endpoints supported - endpoint 0 included * 409615 program memory * 1608 data memory RAM
clock at VDD=5V
* Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * 20/28/48-pin SSOP, 20/32-pin QFN packages
General Description
The HT82B40R and HT82B40A are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, integrated USB interface, Power Down and wake-up functions, Watchdog timer etc, make the devices extremely suitable for use in computer peripheral product applications as well as many other applications such as industrial control, consumer products, subsystem controllers, etc. The HT82B40A mask version type is fully pin and functionally compatible with the HT82B40R OTP version device.
Rev. 1.10
1
September 4, 2009
HT82B40R/HT82B40A
Block Diagram
W a tc h d o g T im e r 8 - b it R IS C MCU C o re O T P P ro g ra m M e m o ry D a ta M e m o ry S ta c k Low V o lta g e R eset W a tc h d o g T im e r O s c illa to r R eset C ir c u it In te rru p t C o n tr o lle r R C /C ry s ta l O s c illa to r
USB I/O P o rts 8 - b it T im e r 1 6 - b it T im e r P r o g r a m m a b le F re q u e n c y G e n e ra to r
V33O
Pin Assignment
PB0 PB2 PB4 PB6 VDD PB6 1 2 3 4 5 6 7 8 9 10 PB7 VDD V33O D -/D A T A D + /C L K PE0 PE1 GND RES 20 19 18 17 16 15 14 13 12 11 PB1 PB0 P A 7 /T M R 1 P A 6 /T M R 0 PA5 PA4 PA3 PA2 PA1 PA0 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NC NC NC NC NC NC VDD V33O PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PB5 PB6 PB7 VDD V33O D -/D A T A D + /C L K PE0 PE1 GND RES PC0 PC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB3 PB2 PB1 PB0 P A 7 /T M R 1 P A 6 /T M R 0 PA5 PA4 PA3 PA2 PA1 PA0 PC7 PC6 D -/D A T A D + /C L K PE0 PE1 GND RES PC0 PC1 PC2 PC3 PD0 PD1 PD2 PD3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 P A 7 /T M R 1 P A 6 /T M R 0 PA5 PA4 PA3 PA2 PA1 PA0 PC7 PC6 PC5 PC4 PD7 PD6 PD5 PD4 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
1 2 3 4 5 6 7 8 9 1011 1213 1415 16
V33 D -/D A T D + /C L PE GN
O K D A
1 2
20 1918 17 16 3
1
4 5
H T82B 40R 14 H T82B 40A 13 2 0 Q F N -A 1 2
6 7 8 9 10 11
15
P A 7 /T M R 1 P A 6 /T M R 0 PA5 PA4 PA3
PA PA PA PC RE S 3 2 1 0
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A 2 0 S S O P -A
PA PA PA PA PA PA P A 6 /T M R P A 7 /T M R 1
32 31 30 29282726 25 24 23 22 21 20 19 18 17
0 H T82B 40R H T82B 40A 3 2 Q F N -A PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 RES GND PE1 PE0 D + /C L K D -/D A T A V33O VDD
5
4
3
2
1
0
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A 2 8 S S O P -A
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A 4 8 S S O P -A
Rev. 1.10
2
September 4, 2009
HT82B40R/HT82B40A
Pin Description
Pin Name I/O Options Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions deterPull-high mine if the pin is a CMOS output or NMOS, PMOS or Schmitt Trigger Wake-up input. Configuration options determine if the structures are CMOS, NMOS/CMOS/PMOS NMOS or PMOS types. Configuration options determine if the pins have pull-high resistors. TMR0 and TMR1 are pin-shared with PA6 and PA7, respectively. Bidirectional 8-bit input/output port. Each nibble can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. The power supply of PB0~PB7 can be optioned as VDD or V33O output. Bidirectional 8-bit input/output port. Each nibble can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Bi-directional 8-bit input/output port. Each nibble can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. Bidirectional 2-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. USBD+ line. USB function is controlled by software control register USBD- line. USB function is controlled by software control register Schmitt trigger reset input. Active low Digital negative power supply, ground Digital positive power supply 3.3V regulator output
PA0~PA5 PA6/TMR0 PA7/TMR1
I/O
PB0~PB7
I/O
Pull-high Wake-up
PC0~PC7
I/O
Pull-high Wake-up
PD0~PD7
I/O
Pull-high Wake-up
PE0~PE1
I/O
Pull-high Wake-up 3/4 3/4 3/4 3/4 3/4 3/4
D+/CLK D-/DATA RES VSS VDD V33O
I/O I/O I 3/4 3/4 O
Note: As the Pin Description table applies to the largest package size not all pin may exist on smaller packages.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
3
September 4, 2009
HT82B40R/HT82B40A
D.C. Characteristics
Test Conditions Symbol VDD IDD Parameter VDD Operating Voltage (Crystal OSC) Operating Current 3/4 5V Conditions fSYS=6MHz or 12MHz No load, fSYS=6MHz No load, fSYS=12MHz Standby Current ISTB Standby Current (WDT Enabled) Input Low Voltage for PA, PC VIL Input Low Voltage for PB Input Low Voltage for RES pin Input High Voltage for PA, PC VIH Input High Voltage for PB Input High Voltage for RES pin VLVR VV33O IOL1 IOL2 IOL3 IOH1 IOH2 IOH3 Low Voltage Reset 3.3V Regulator Output for USB SIE Output Sink Current for Port PB Output Sink Current for Port PA0 Output Sink Current for Port PA1~PA7,PC, PD and PE0~PE1 Output Source Current for Port PB Output Source Current for Port PA0 Output Source Current for Port PA1~PA7,PC,PD and PE0~PE1 Pull-high Resistance for CLK, DATA RPH Pull-high Resistance for PB Pull-high Resistance for PA, PC, PD and PE0~PE1 Note: * include 15kW loading on the USBD+, USBD- lines at the host terminal. 5V 3/4 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V where VDDIO=VDD or V33O by option for PB 5V NO load, system USB suspend, set CLK_adj [22H] * No load, system HALT, input/output mode, set SUSP2 & CLK_adj [22H] 3.3 3/4 3/4 3/4 3/4 6.5 7.5 3/4 5.5 12 16 400 V mA mA mA Min. Typ. Max. Unit Ta=25C
3/4 0 0 0
3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.6 3.3 20 12 4 -40 -20 -4 4.7 30 50
15 0.8 0.3VDDIO 0.4VDD 5 VDDIO VDD 3.2 3.6 3/4 3/4 3/4 3/4 3/4 3/4 3/4 45 70
mA V V V V V V V V mA mA mA mA mA mA kW kW kW
2 where VDDIO=VDD 0.8VDDIO or V33O by option for PB 0.9VDD 3/4 IV33O=70mA VOL=0.4V VOL=0.4V VOL=0.4V VOH=3.4V VOH=3.4V VOH=3.4V 2.0 3.0 10 6 2 -20 -10 -2 3/4 15 20
Rev. 1.10
4
September 4, 2009
HT82B40R/HT82B40A
A.C. Characteristics
Test Conditions Symbol fRCSYS tWDT Parameter VDD RC Clock with 8-bit Prescaler Register Watchdog Time-out Period (System Clock) USBD+, USBD- Rising & Falling Time tOST Oscillation Start-up Timer Period 5V 3/4 3/4 3/4 3/4 4.0V~ 5.5V 3.0~ 4.0V 4.2~ 5.5V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1024 75 3/4 3/4 10.80 10.56 11.82 32 3/4 3/4 1024 5 12.00 12.00 12.00 3/4 3/4 300 3/4 3/4 13.20 13.44 12.18 kHz 1/fRCSYS ns tSYS ms MHz MHz MHz Min. Typ. Max. Unit Ta=25C
tOSCsetup Crystal Setup fINO125V fINO123V fINOUSB Note: Internal Oscillator Frequency for 12MHz Internal Oscillator Frequency for 12MHz Internal Oscillator Frequency with USB Mode
tSYS=1/fSYS Power_on period = tWDT + tOST + tOSCsetup WDT Time_out in Normal Mode = 1/ fRCSYS 256 WDTS + tWDT WDT Time_out in Power Down Mode = 1/ fRCSYS 256 WDTS + tOST + tOSCsetup Trimmed for 5V operation using factory trim values. Frequency Trim to 12MHz 3%
Rev. 1.10
5
September 4, 2009
HT82B40R/HT82B40A
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The system clock is derived from an internal oscillator and is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.
O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.10
6
September 4, 2009
HT82B40R/HT82B40A
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
B o tto m
o f S ta c k
S ta c k L e v e l 8
Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Mode Initial Reset USB Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter Bits b11 0 0 0 0 b10 0 0 0 0 b9 0 0 0 0 b8 0 0 0 0 PC8 #8 S8 b7 0 0 0 0 @7 #7 S7 b6 0 0 0 0 @6 #6 S6 b5 0 0 0 0 @5 #5 S5 b4 0 0 0 0 @4 #4 S4 b3 0 0 1 1 @3 #3 S3 b2 0 1 0 1 @2 #2 S2 b1 0 0 0 0 @1 #1 S1 b0 0 0 0 0 @0 #0 S0
Program Counter + 2 PC11 PC10 PC9 #11 S11 #10 S10 #9 S9
Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits @7~@0: PCL bits S11~S0: Stack register bits
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
000H 004H 008H 00CH
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
In itia lis a tio n V e c to r USB In te rru p t V e c to r T im e r /E v e n t 0 C o u n te r In te rru p t V e c to r T im e r /E v e n t 1 C o u n te r In te rru p t V e c to r
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The HT82B40R is a One-Time Programmable, OTP, memory type device where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The HT82B40A is a Mask memory type device and offers the most cost effective solution for high volume products. Structure The Program Memory has a capacity of 4K by 15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
FFFH
1 5 b its
Program Memory Structure
* Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program jumps to this location and begins execution.
* Table location
Any location in the program memory can be used as look-up tables. There are three methods to read the Program Memory data using two table read instructions: TABRDC and TABRDL, transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows:
Using the instruction TABRDC [m] for the current Program Memory page, where one page= 256words, where the table location is defined by TBLP in the current page. This is where the configuration option has disabled the TBHP register. Using the instruction TABRDC [m], where the table location is defined by registers TBLP and TBHP. Here the configuration option has enabled the TBHP register. Using the instruction TABRDL [m], where the table location is defined by registers TBLP in the last page which has the address range 0F00H~0FFFH.
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program jumps to this location and begins execution.
* Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program jumps to this location and begins execution. Instruction b11 TABRDC [m] TABRDL [m] PC11 1 b10 PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointers, TBLP and TBHP, are read/write registers, which indicate the table location. Before accessing the the table, the locations must be placed Table Location Bits b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
@6 @6
Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits Rev. 1.10 8 September 4, 2009 TBHP register Bit 3 ~ Bit 0 when TBHP is enabled.
HT82B40R/HT82B40A
in the TBLP and TBHP registers (if the configuration option has disabled TBHP then the value in TBHP has no effect). TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR and errors can occur. Using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Once TBHP is enabled, the instruction TABRDC [m] reads the Program Memory data as defined by the TBLP and TBHP values. If the Program Memory code option has disabled TBHP, the instruction TABRDC [m] reads the Program Memory data as defined by TBLP only in the current Program Memory page. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the TBLP register and the higher order address in the TBHP register. These two registers define the full address of the look-up table. Using the TBHP must be selected by configuration option, if not used table data can still be accessed but only the lower byte address in the current page or last page can be defined. After setting up the table pointers, the table data can be retrieved from the current Program Memory page or last Program Memory page using the TABRDC[m] or TABRDL [m] instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is F00H which refers to the start address of the last page within the 4K Program Memory of device. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address F06H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed.
P ro g ra m C o u n te r H ig h B y te TBLP
P ro g ra m M e m o ry
TBHP TBLP
P ro g ra m M e m o ry
TBLH T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Table Read - TBLP only
Table Read - TBLP/TBHP
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
tempreg1 db tempreg2 db : : mov a,06h mov tblp,a : : tabrdl dec tblp tabrdl tempreg2 tempreg1 ? ? ; temporary register #1 ; temporary register #2
; initialise table pointer - note that this address is referenced ; to the last page or present page
; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address F06H transferred to tempreg1 and TBLH ; reduce value of table pointer by one ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : org F00h dc
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : mon to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the SET [m].i and CLR [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
00H Spec P u rp o Da M em o ia l se ta ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry DFH
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide. The start address of the Data Memory for all devices is the address 00H. Registers which are comRev. 1.10 10 Note:
Data Memory Structure Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP.
September 4, 2009
HT82B40R/HT82B40A
Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. It is divided into two banks, Bank 0 and Bank1. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H. The Special Purpose Registers for the USB interface are stored in Bank 1 which can only be accessed by first setting the Bank Pointer to a value of 01H and then using Indirect Addressing Register IAR1 and Memory Pointer MP1. Bank 1 can only be accessed indirectly using the MP1 Memory Pointer, direct addressing is not possible.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1D H 1EH 1FH 20H 21H 22H 23H nk0 R0 P0 R1 P1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PE PEC Ba IA M IA M 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH B ank1 U SB_STAT P IP E _ C T R L AW R STALL P IP E S IE S M IS C END PT_EN F IF O 0 F IF O 1 F IF O 2
Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointer - MP0, MP1 For all devices, two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access both banks.
: U n u s e d re a d a s "0 "
TB U U S
HP SC SR CC
Special Purpose Data Memory
Rev. 1.10
11
September 4, 2009
HT82B40R/HT82B40A
data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov loop: clr inc sdz jmp a,04h block,a a,offset adres1 mp0,a IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared
continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH, TBHP These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their values can be changed, for example using the INC or DEC instructions, allowing for easy table Rev. 1.10 12 data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. September 4, 2009
HT82B40R/HT82B40A
b7 TO PDF OV Z AC b0 C
S T A T U S R e g is te r
Ar Ca Au Ze ith m e r r y fla x ilia r y r o fla g O v e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
Timer/Event Counter Registers TMR0, TMR0C, TMR1H, TMR1L, TMR1C Both devices possess a single internal 8-bit count-up timer. An associated register known as TMR0 is the location where the timers 8-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMR0C, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. All devices possess one internal 16-bit count-up timer. An associated register pair known as TMR1L/TMR1H is the location where the timer 16-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control register, known as TMR1C, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, PD and PE0~PE1. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC, PDC and PEC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the 13 September 4, 2009
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Interrupt Control Registers - INTC The microcontrollers provide two internal timer/event counter overflow interrupts and one USB interrupt. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction.
Rev. 1.10
HT82B40R/HT82B40A
SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Bank Pointer - BP The Special Purpose Data Memory is divided into two Banks, Bank 0 and Bank 1. The USB control registers are located in Bank 1, while all other registers are located in Bank 1. The Bank Pointer selects which bank data is to be accessed from. If Bank 0 is to be accessed then BP must be set to a value of 00H, while if Bank 1 is to be accessed then BP must be set to a value of 01H.
b7 b0 BP0 B a n k P o in te r BP0 0 1 D a ta M e m o ry Bank 0 Bank 1
Port A CMOS/NMOS/PMOS Structure The pins on Port A can be setup via configuration option to be either CMOS, NMOS or PMOS types. Port B VDD/V33O Option Structure The power supply for the Port B pins can be setup via configuration option to be either VDD or V33O. Port Pin Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the port pin changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on PA, PB, PC, PD and PE0~PE1 has the capability to wake-up the device on an external falling edge. Note that some pins can only be setup nibble wide whereas other can be bit selected to have a wake-up function. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC, PDC and PEC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each of the I/O ports is directly mapped to a bit in its associated port control register. Note that several pins can be setup to have NMOS outputs using configuration options. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as an output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which package is chosen, the microcontroller provides up to 34 bidirectional input/output lines labeled with port names PA, PB, PC, PD and PE0~PE1. These I/O ports are mapped to the Data Memory with addresses as shown in the Special Purpose Data Memory table. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS transistors. A pin or nibble option on the I/O ports can be selected to select pull-high Resistors.
Rev. 1.10
14
September 4, 2009
HT82B40R/HT82B40A
Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* External Timer0 Clock Input
Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the PAC, PBC, PCC, PDC and PEC port control register, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated PA, PB, PC, PD and PE port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
The external timer pin TMR0 is pin-shared with the I/O pin PA6. To configure this pin to operate as timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, this pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.
* External Timer1 Clock Input
The external timer pin TMR1 is pin-shared with the I/O pin PA7. To configure this pin to operate as timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, this pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation I/O Pin Structures The diagram illustrates a generic I/O pin internal structures. As the exact logical construction of the I/O pin will differ and as the pin-shared structures are not illustrated this diagram is supplied as a guide only to assist with the functional understanding of the I/O pins.
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing All pins have the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port pins. Single or multiple pins can be setup to have this function.
V C o n tr o l B it
DD
/V 3 3 O
(P B )
D a ta B u s
D
Q CK S Q
P u ll- H ig h O p tio n
W eak P u ll- u p
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
I/O D a ta B it Q D CK Q S M U X
p in
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
W a k e - u p O p tio n
Input/Output Ports
Rev. 1.10
15
September 4, 2009
HT82B40R/HT82B40A
Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. This device contains two count-up timers of 8-bit and 16-bit capacities respectively. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the Timer/Event Counter and into which an initial value can be preloaded, and is known as TMR0, TMR1H or TMR1L. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register, which defines the timer options and determines how the Timer/Event Counter is to be used, and has the name TMR0C or TMR1C. This device can have the timer clocks configured to come from the internal clock sources. In addition, the timer clock source can also be configured to come from the external timer pins. The external clock source is used when the Timer/Event Counter is in the event counting mode, the clock source being provided on the external timer pin. The pin has the name TMR0 or TMR1 and is pin-shared with an I/O pin. Depending upon the condition of the T0E or T1E bit in the Timer Control Register, each high to low, or low to high transition on the external timer input pin will increment the Timer/Event Counter by one. Configuring the Timer/Event Counter Input Clock Source The Timer/Event Counters clock can originate from various sources. The system clock source is used when the Timer/Event Counter 0 is in the timer mode or in the pulse width measurement mode. The instruction clock source (system clock source divided by 4) is used when the Timer/Event Counter 1 is in the timer mode or in the pulse width measurement mode. The external clock source is used when the Timer/Event Counter is in the event counting mode, the clock source being provided on the external timer pin, TMR0 or TMR1. Depending upon the condition of the T0E or T1E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Timer Register - TMR0, TMR1L/TMR1H The timer registers are special function registers located in the Special Purpose RAM Data Memory and are the places where the actual timer values are stored. For 8-bit Timer/Event Counter 0, this register is known as TMR0. For 16-bit Timer/Event Counter 1, the timer registers are known as TMR1L and TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition ocRev. 1.10 16 curs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note when using instructions to preload data into the low byte timer register, namely TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte timer register. The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. At the same time the data in the low byte buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. It must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Register - TMR0C/TMR1C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. For devices are two timer control registers known as TMR0C, TMR1C . It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control September 4, 2009
HT82B40R/HT82B40A
D a ta B u s P r e lo a d R e g is te r T0M 1 T0M 0 T im e r /E v e n t C o u n te r T0O N 8 - B it T im e r /E v e n t C o u n te r R e lo a d
TM R0 T0E
fS
YS
/4
T im e r /E v e n t C o u n te r M o d e C o n tro l
O v e r flo w to In te rru p t
8-bit Timer/Event Counter 0 Structure
D a ta B u s L o w B y te B u ffe r 1 6 - B it P r e lo a d R e g is te r R e lo a d
T1M 1 fS T1E
YS
T1M 0
TM R1
/4
T im e r /E v e n t C o u n te r M o d e C o n tro l T1O N
H ig h B y te
Low
B y te
1 6 - B it T im e r /E v e n t C o u n te r
O v e r flo w to In te rru p t
16-bit Timer/Event Counter 1 Structure
b7 T0M 1 T0M 0 T0O N T0E b0 TM R0C R e g is te r
N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 0 a c tiv e e d g e s e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e T im e r /E v e n t C o u n te r 0 C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c TM 2TM 1 TM 2TM 0 no 0 0 ev 1 0 tim 0 1 1 1 pu t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b7 T1M 1 T1M 0 T1O N T1E b0 TM R1C R e g is te r
N o t im p le m e n te d , r e a d a s " 0 " T im e r /E v e n t C o u n te r 1 a c tiv e e d g e s e le c t 1 : c o u n t o n fa llin g e d g e 0 : c o u n t o n r is in g e d g e T im e r /E v e n t C o u n te r 1 c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g m o d e s e le c TM 2TM 1 TM 2TM 0 no 0 0 ev 1 0 tim 0 1 1 1 pu t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
Rev. 1.10
17
September 4, 2009
HT82B40R/HT82B40A
register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as T0E or T1E, depending upon which timer is used. Configuring the Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode Bit7 Bit6 1 0 value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Bit7 Bit6 0 1
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run.Each time an internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the
In this mode, the external timer pin, TMR0 or TMR1, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit T0E or T1E, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that
P r e s c a le r O u tp u t
In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Rev. 1.10
18
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HT82B40R/HT82B40A
the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Power Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. Configuring the Pulse Width Measurement Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct valueas shown. Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode Bit7 Bit6 1 1 pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second is to ensure that the port control register configures the pin as an input.ot by the logic level.
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the other bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. If the Active Edge Select bit T0E or T1E, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, TMR0 or TMR1, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer
E x te r n a l T im e r P in In p u t T0O N orT1O N ( w ith T 0 E o r T 1 E = 0 ) P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3 +4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
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I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external TMR0 and TMR1 pins for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register bits for these pins must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on these pins will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.
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org 04h ; USB interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmr0int ; jump here when Timer0 overflows : org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine Tmr0int: : ; Timer/Event Counter 0 main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr0,a; mov a,080h ; setup Timer control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmr0c.4 ; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
Interrupts are an important part of any microcontroller system. When an internal function such as a Timer/Event Counter overflow or a USB interrupt occur, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. while the internal interrupts are controlled by the Timer/Event Counter overflow, USB interrupt or reception. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by an interrupt control register. By controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation When a USB interrupt occurs or one of the Timer/Event Counters overflow, if their appropriate interrupt enable bit is set, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
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b7 T1F T0F USBF ET1I ET0I EUI b0 EMI IN T C R e g is te r
M a s te r in te r r u p t g lo b a l e n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le U S B in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le 1 : e n a b le 0 : d is a b le U S B in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g 1 : a c tiv e 0 : in a c tiv e F o r te s t m o d e u s e d o n ly M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
INTC Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e U S B In te rru p t R e q u e s t F la g U S B F T im e r /E v e n t C o u n te r 0 O v e r flo w In te r r u p t R e q u e s t F la g T 0 F T im e r /E v e n t C o u n te r 1 O v e r flo w In te r r u p t R e q u e s t F la g T 1 F F IF O
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0I
In te rru p t P o llin g Low
ET1I
Interrupt Structure
Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB Interrupt Timer/Event Counter 0 Overflow Interrupt Timer/Event Counter 1 Overflow Interrupt Priority 1 2 3 Vector 0004H 0008H 000CH
have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ET0I/ET1I, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter interrupt request flag, T0F/T1F, is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H/0CH, will take place. When the interrupt is serviced, the timer interrupt request flag, T0F/T1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
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Programming Considerations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. USB Interrupt The USB interrupts are triggered by the following USB events causing the related interrupt request flag, USBF, to be set.
* Access of the corresponding USB FIFO from PC * A USB suspend signal from the PC * A USB resume signal from the PC * A USB Reset signal
power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
When the interrupt is enabled, the stack is not full and the USB interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, USBF, and the EMI bit will be cleared to disable other interrupts. When the PC Host accesses the FIFO of the device, the corresponding request bit, USR, is set, and a USB interrupt is triggered. So the user can easy determine which FIFO has been accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the device receive a USB Suspend signal from Host PC, the suspend line (bit0 of USC) is set and a USB interrupt is also triggered. Also when device receive a Resume signal from Host PC, the resume line (bit3 of USC) is set and a USB interrupt is triggered.
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a proper reset operation. In such cases it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
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VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
* Low Voltage Reset - LVR
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
VDD
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart
* Watchdog Time-out Reset during Power Down
0 .1 m F VSS
Enhanced Reset Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point. Note that as the external reset pin is also pin-shared with PA7, if it is to be used as a reset pin, the correct reset configuration option must be selected.
RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
tR
S S T T im e - o u t In te rn a l R e s e t
STD
WDT Time-out Reset during Normal Operation Timing Chart
tR
STD
RES Reset Timing Chart
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Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 0 1 1 0 0 0 u 1 RESET Conditions RES reset during power-on RES wake-up during Power Down RES or LVR reset during normal operation WDT time-out reset during normal operation WDT time-out reset during Power Down Prescaler Timer/Event Counter The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off The Timer Counter Prescaler will be cleared
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
Note: u stands for unchanged
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. Register MP0 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC Reset (Power-on) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx 1000 0111 --00 xxxx -000 0000 xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 1000 0111 --1u uuuu -000 0000 xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 RES Reset (Normal Operation) xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 1000 0111 --00 uuuu -000 0000 xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 RES Reset (HALT) xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 1000 0111 --00 uuuu -000 0000 xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu 00u0 00uu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset USB Reset (Normal) (HALT) xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 1000 0111 --uu uuuu -000 0000 xxxx xxxx uu-u u--uuuu uuuu uuuu uuuu uu-u u--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 1000 0111 --01 uuuu -000 0000 xxxx xxxx uu-u u--uuuu uuuu uuuu uuuu uu-u u--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
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Reset (Power-on) 1111 1111 1111 1111 ---- --11 ---- --11 xxxx xxxx 1000 0000 ---- 0000 0000 0000 --xx 0000 0000 0110 0000 0000 ---- 0000 0000 0000 00-0 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx WDT Time-out (Normal Operation) 1111 1111 1111 1111 ---- --11 ---- --11 uuuu uuuu uuuu xuux ---- uuuu uuuu uuuu --xx 0000 uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uu-x xuuu xxuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx RES Reset (Normal Operation) 1111 1111 1111 1111 ---- --11 ---- --11 uuuu uuuu 1000 0000 ---- 0000 0000 0000 --xx 0000 0000 0110 0000 0000 ---- 0000 0000 0000 00-0 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx RES Reset (HALT) 1111 1111 1111 1111 ---- --11 ---- --11 uuuu uuuu 1000 0000 ---- 0000 0000 0000 --xx 0000 0000 0110 0000 0000 ---- 0000 0000 0000 00-0 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu ---- --uu ---- --uu uuuu uuuu uuuu xuux ---- uuuu uuuu uuuu --xx 0000 uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uu-x xuuu xxuu uuuu uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx USB Reset USB Reset (Normal) (HALT) 1111 1111 1111 1111 ---- --11 ---- --11 uuuu uuuu 1uuu 0100 ---- 0000 0uu0 u000 --xx 0000 0000 0110 0000 0000 ---- 0000 0000 0000 00-0 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 ---- --11 ---- --11 uuuu uuuu 1uuu 0100 ---- 0000 0uu0 u000 --xx 0000 0000 0110 0000 0000 ---- 0000 0000 0000 00-0 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx
Register PD PDC PE PEC TBHP USC USR SCC USB_STAT PIPE_CTRL AWR STALL PIPE SIES MISC ENDPT_EN FIFO0 FIFO1 FIFO2 Note:
* means warm reset - not implemented u means unchanged x means unknown
Oscillator
The clock source for these devices is provided by an integrated oscillator requiring no external components. This oscillator has two fixed frequencies of either 6MHz, or 12MHz, the selection of which is made by the SYSCLK bit in the SCC register. Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.
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Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
some power. For power sensitive applications it may be therefore preferable to use the system clock source for the Watchdog Timer. If any I/O pins are configured as A/D analog inputs using the channel configuration bits in the ADCR register, then the A/D converter will be turned on and a certain amount of power will be consumed. It may be therefore desirable before entering te Power Down Mode to ensure that the A/D converter is powered down by ensuring that any A/D input pins are setup as normal logic inputs with pull-high resistors. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT or RTC oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. If the configuration options have enabled the Watchdog Timer internal oscillator then this will continue to run when in the Power Down Mode and will thus consume Rev. 1.10 27
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No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. Once the internal WDT oscillator (RC oscillator normally with a period of 78ms) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By using the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2, 1, 0 of the WDTS) can give different time-out periods. If WDTS2, WDTS1, WDTS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6s. If the WDT oscillator is disabled, the WDT clock source may still come from the instruction clock and operate in the same manner except that in the Power down Mode state the WDT may stop counting and lose its protecting purpose. In this situation the WDT logic can be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
Watchdog Timer
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), enabled using a configuration option. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. If the Watchdog Timer is disabled, all the executions related to the WDT results in no operation.
CLR CLR
W D T 1 F la g W D T 2 F la g
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r (
1 o r 2 In s tr u c tio n s fS
YS
/4
CLR 7 - b it P r e s c a le r
W D T O s c illa to r W D T C lo c k S o u r c e
256)
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Bit No.
Label
Function Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, division ratio = 1:1 Bit 2,1,0 = 001, division ratio = 1:2 Bit 2,1,0 = 010, division ratio = 1:4 Bit 2,1,0 = 011, division ratio = 1:8 Bit 2,1,0 = 100, division ratio = 1:16 Bit 2,1,0 = 101, division ratio = 1:32 Bit 2,1,0 = 110, division ratio = 1:64 Bit 2,1,0 = 111, division ratio = 1:128 Bit3=1, D+, and D- connected to 510kW pull-high resistor Bit3=0, No pull-high - default at MCU reset Not used Bit7=1, USB reset signal can reset MCU and set URST_FLAG (bit 2 of 1AH) (default on at MCU reset) Bit7=0, USB reset signal cannot reset MCU WDTS Register
0 1 2
WDTS0 WDTS1 WDTS2
3 4~6 7
WDTS3 3/4 WDTS7
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Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the device will go into a suspend mode. The Suspend line (bit 0 of the USC register) will be set to 1 and a USB interrupt is triggered to indicate that the devices should jump to the suspend state to meet the 500mA USB suspend current spec. In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the USBCKEN bit which is bit3 of the SCC register to 0. The suspend current is 400mA. The user can further decrease the suspend current to 250mA by setting the SUSP2 bit which is bit4 of the SCC register. If in the USB mode set this bit LVR OPT must disable. When the resume signal is sent out by the host, the devices will wake up the MCU with a USB interrupt and the Resume line (bit 3 of the USC register) is set. In order to make the device function properly, the firmware must set the USBCKEN (bit 3 of the SCC register) to 1 and clear the SUSP2 (bit4 of the SCC register). Since the Resume signal will be cleared before the Idle signal is sent out by the host, the Suspend line (bit 0 of the USC register) will be set to 0. So when the MCU is detecting the Suspend line (bit0 of USC register), the Resume line condition should be noted and taken into consideration. After finishing the resume signal, the suspend line will go inactive and a USB interrupt will be triggered. The following is the timing diagram.
SUSPEND U S B R e s u m e S ig n a l
To Configure as PS2 Device The devices can also be configured as a USB interface or PS2 interface device, by configuring SPS2 (bit 4 of the USR register) and SUSB (bit 5 of the USR register). If SPS2=1, and SUSB=0, the device will be configured as a PS2 interface, pin USBD- is configured as a PS2 Data pin and USBD+ is configured as a PS2 Clk pin. The user can read or write to the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of the USC register), PS2CKI (bit 5 of the USC register), PS2DAO (bit 6 of the USC register) and S2CKO (bit 7 of the USC register) respectively. The user should make sure that in order to read the data properly, the corresponding output bit must be set to 1. For example, if it is desired to read the PS2 Data by reading PS2DAI, then PS2DAO should set to 1. Otherwise it is always read as 0. If SPS2=0, and SUSB=1, the device is configured as a USB interface. Both the USBD- and USBD+ is driven by the SIE of the HT82B40R/ HT82B40A . The user can only write or read the USB data through the corresponding FIFO. Both the SPS2 and SUSB default is 0. USB Interface There are eleven registers used for the USB function. The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the USB command is not to be loaded into this register until the SETUP stage is completed. Bit No. 0 7~1 Label WKEN AD6~AD0 R/W W W Function Remote wake-up enable/disable USB device address
U S B _ IN T
AWR (42H) Register
As the device has a remote wake up function it can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC register). Once the USB Host receives a wake-up signal from the devices, it will send a Resume signal to the device. The timing is as follows:
SUSPEND M in . 1 USB CLK RMW K U S B R e s u m e S ig n a l M in . 2 .5 m s
U S B _ IN T
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Bit No. 0 Label SUSPEND R/W R Function Read only, USB suspend indication. When this bit is set to 1 (set by the SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered on any change of this bit. USB remote wake up command. Set by the MCU to force the USB host to leave the suspend mode. When this bit is set to 1, a 2ms delay for clearing this bit to 0 is needed to insure the RMWK command is accepted by SIE.
1
RMOT_ WK
W
2
URST_ FLAG
USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect which bus (PS2 or USB) is attached. When the URST is set to 1, this indiR/W cates that a USB reset has occurred (the attached bus is USB) and a USB interrupt will be initialised. USB resume indication. When the USB leaves the suspend mode, this bit is set to 1 (set by the SIE). This bit will appear for 20ms waiting for the MCU to detect. When the RESUME is set by the SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set the USBCKEN and clear SUSP2 (in the SCC register) to enable the SIE detect function. The RESUME will be cleared while SUSP is going to 0. When the MCU is detecting the SUSP, the condition of RESUME (which wakes-up the MCU ) should be noted and taken into consideration. Read only, USBD-/DATA input Read only, USBD+/CLK input Data for driving the USBD-/DATA pin when working under 3D PS2 mouse function. (Default=1) Data for driving the USBD+/CLK pin when working under 3D PS2 mouse function. (Default=1) USC (20H) Register
3
RESUME_O
R
4 5 6 7
PS2_DAI PS2_CKI PS2_DAO PS2_CKO
R R W W
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus, PS2 or USB. The endpoint request flags, EP0IF, EP1IF and EP2IF, are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur, if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is served, the endpoint request flag has to be cleared to 0. Bit No. 0 Label EP0_INT R/W Function
When this bit is set to 1 (set by the SIE), it indicates that endpoint 0 is accessed R/W and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by the SIE), it indicates that endpoint 1 is accessed R/W and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. When this bit is set to 1 (set by the SIE), it indicates that endpoint 2 is accessed R/W and a USB interrupt will occur. When the interrupt has been served, this bit should be cleared by firmware. 3/4 Reserved
1
EP1_INT
2 3, 6
EP2_INT 3/4
4 5
00 : Non-USB mode, turn-off V33O, both D+and D- can be read and write - default 01 : Non-USB mode, has 200 ohm between VDD and V33O, both D+and D- can be MODE_CTRL0 read and write R/W MODE_CTRL1 10 : USB mode, 1.5K ohm between D- and V33O, V33O output 3.3V, both D+and D- are read only 11 : Non-USB mode, V33O output 3.3V, both D+and D- can be read and write USB_flag R/W This flag is used to indicate that the MCU is in the USB mode - Bit=1 This bit is R/W by FW and will be cleared to 0 after power-on reset - Default=0 USR (21H) Register
7
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There is a system clock control register implemented to select the clock used in the MCU. This register consists of the USB clock control bit, USBCKEN, second suspend mode control bit, SUSP2, and a system clock selection bit, SYSCLK. The PS2 mode indicate bit, PS2_flag, and a system clock adjust control bit, CLK_adj. Bit No. 0, 1, 2 3 Label 3/4 R/W 3/4 Reserved bit set 0 USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=0) When set to 1, turn-off Band-gap circuit. Default value is 0. In the Power-down Mode this bit should be set high to reduce power consumption.The LVR has no function. In the USB mode this bit cannot be set high. This flag is used to indicate that the MCU is in the PS2 mode. (Bit=1) This bit is R/W by FW and will be cleared to 0 after power-on reset. (Default=0) Function
USBCKEN R/W 3/4 R/W
4
SUSP2
5
PS2_flag
6
SYSCLK
This bit is used to specify the system oscillator frequency used by the MCU. If a 6MHz R/W crystal oscillator or resonator is used, this bit should be set to 1. If a 12MHz crystal oscillator or resonator is used, this bit should be cleared to 0 (default). This bit is used to adjust the system clock for the USB mode for temperature changes. In the Power-down Mode this bit should be set high to reduce power consumption. R/W 0: enable (default) 1: disable SCC (22H) Register
7
CLK_adj
STALL and PIPE, PIPE_CTRL, Endpt_EN Registers The PIPE register represents whether the corresponding endpoint is accessed by the host or not. After an ACT_EN signal has been sent out, the MCU can check which endpoint had been accessed. This register is set only after the a time when the host is accessing the corresponding endpoint. The STALL register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set. The PIPE_CTRL Register is used for configuring the IN (Bit=1) or OUT (Bit=0) Pipe. The default is define IN pipe. Bit0 (DATA0) of the PIPE_CTRL Register is used to set the data toggle of any endpoint (except endpoint 0) using data toggles to the value DATA0. Once the user wants any endpoint (except endpoint 0) using data toggles to the value DATA0. the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycles. The Endpt_EN Register is used to enable or disable the corresponding endpoint (except endpoint 0) Enable Endpoint (Bit=1) or disable Endpoint (Bit=0) The bitmaps are list are shown in the following table: Register Name PIPE_CTRL STALL PIPE Endpt_EN R/W R/W R/W R R/W Register Address 01000001B 01000011B 01000100B 01000111B Bit7~Bit3 Reserved 3/4 3/4 3/4 3/4 Bit 2 Pipe 2 Pipe 2 Pipe 2 Pipe 2 Bit 1 Pipe 1 Pipe 1 Pipe 1 Pipe 1 Bit 0 DATA0 Pipe 0 Pipe 0 Pipe 0 Default Value 00000111 00000111 00000000 00000111
PIPE_CTRL (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers The USB_STAT Register (40H) is used to indicate the present USB signal state. Bit No. 0 1 2 3 4 5~7 Function EOP J_state K_state SE0 SE1 3/4 Read/Write R/W R/W R/W R/W R/W 3/4 USB_STAT (40H) Register Table 01000000B Register Address
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Func. Name EOP J_state K_state 3/4 SE0 SE1 R/W R/W R/W R/W 3/4 R/W R/W Description This bit is used to indicate the SIE has detected a EOP USB signal in the USB Bus. This bit is set by SIE and cleared by F/W. This bit is used to indicate the SIE has detected a J_state USB signal in the USB Bus. This bit is set by SIE and cleared by F/W. This bit is used to indicate the SIE has detected a K_state USB signal in the USB Bus. This bit is set by SIE and cleared by F/W. Unused bit, read as 0 This bit is used to indicate the SIE has detected a SE0 noise in the USB Bus. This bit is set by SIE and cleared by F/W. This bit is used to indicate the SIE has detected a SE1 noise in the USB Bus. This bit is set by SIE and cleared by F/W. USB_STAT Function Table The SIES Register is used to indicate the present signal state in which the SIE receives and also defines whether the SIE has to change the device address automatically. Bit No. 0 1 2~6 7 Function Adr_set F0_ERR 3/4 MNI Read/Write R/W R/W 3/4 R/W SIES (45H) Register Table Func. Name R/W Description This bit is used to configure the SIE to automatically change the device address with the value of the Address+Remote_WakeUp Register. When this bit is set to 1 by F/W, the SIE will update the device address with the value of the Address+Remote_WakeUp Register after the PC Host has successfully read the data from the device by the IN operation. The SIE will clear the bit after updating the device address. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register. Default 0. This bit is used to indicate that some errors have occurred when accessing the FIFO0. This bit is set by SIE and cleared by F/W. Default 0 Unused bit, read as 0 This bit is used to control whether the USB interrupt is output to the MCU in a NAK response to the PC Host IN or OUT token. Only for Endpoint0 1: has only USB interrupt, data is transmitted to the PC host or data is received from the PC Host 0: always has USB interrupt if the USB accesses FIFO0 Default 0 SIES Function Table 01000001B Register Address
ADR_ SET
R/W
F0_ERR 3/4
R/W 3/4
NMI
R/W
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The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the desired endpoint FIFO. The MISC will be cleared by the USB reset signal. Bit No. 0 Label REQ R/W R/W Function After setting the other status of the desired one in the MISC, endpoint FIFO can be requested by setting this bit to 1. After the task is completed, this bit must be cleared to 0. This bit defines the direction of data transferring between the MCU and endpoint FIFO. When the TX is set to 1, this means that the MCU wants to write data to the endpoint FIFO. After the task is completed, this bit must be cleared to 0 before terminating the request to represent the end of transferring. For a read action, this bit has to be cleared to 0 to represent that MCU wants to read data from the endpoint FIFO and has to be set to 1 after completion. Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready. Defines which endpoint FIFO is selected, SELP1,SELP0: 00: endpoint FIFO0 01: endpoint FIFO1 10: endpoint FIFO2 11: reserved Used to show that the data in the endpoint FIFO is a SETUP command. This bit has to be cleared by firmware. That is to say, even if the MCU is busy, the device will not miss any SETUP commands from the host. Read only status bit, this bit is used to indicate that the desired endpoint FIFO is ready for operation. Used to indicate that a 0-sized packet has been sent from a host to the MCU. This bit should be cleared by firmware. MISC (46H) Register The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which the address is listed in the following table. After reading the current data, the next data will show after 2ms, this is used to check the endpoint FIFO status and response to the MISC register, if the read/write action is still going on. Registers FIFO0 FIFO1 FIFO2 R/W R/W R/W R/W Bank 1 1 1 Address 48H 49H 4AH Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0
1
TX
R/W
2
CLEAR
R/W
4 3
SELP1 SELP0
R/W
5
SCMD
R/W
6 7
READY LEN0
R R/W
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 can be read or not Check whether FIFO1 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO1 Note: MISC Setting Flow and Status 00H(R)01H(R)delay 2ms, check 41H(R)read* from FIFO0 register and check not ready (01H)(R)03H(R)02H 0AH(R)0BH(R)delay 2ms, check 4BH(R)write* to FIFO1 register and check not ready (0BH)(R)09H(R)08H 00H(R)01H(R)delay 2ms, check 41H (ready) or 01H (not ready)(R)00H 0AH(R)0BH(R)delay 2ms, check 4BH (ready) or 0BH (not ready)(R)0AH 00H(R)01H(R)delay 2ms, check 81H(R)read once (01H)(R)03H(R)02H 0AH(R)0BH(R)delay 2ms, check 0BH(R)0FH(R)0DH(R)08H
*: There is a 2ms time between 2 read actions or between 2 write actions.
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Table High Byte Pointer for Current Table Read TBHP (Address 0X1F) Register TBHP (0X1F) Bits 3~0 Labels PGC3~PGC0 Read/Write R Option 3/4 Functions Store current table read bit11~bit8 data
Configuration Options
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PA0~7 Pull-high by bit (default Pull-high) PB, PC, PD wake-up by nibble (default Pull-high) PB, PC, PD Pull-high by nibble (default Pull-high) 2.4 V (error 0.2V)LVR enable/disable (default enable) WDT function: enable, disable for normal mode (default enable) WDT clock source: RC; (system /4) (default T1) CLRWDT instruction is by 1 or 2 PA output mode (CMOS/NMOS/PMOS) by bit (default CMOS) PA0~7 wake-up by bit, (default enable) TBHP enable /disable (default disable) PE0, PE1 Pull-high by bit PE0, PE1 wake-up by bit PB0~7 VDD :5V (default) PB0~7 VDD :V33O V33O regulator output Options
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Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications for HT82B40R
PA0~PA7
VDD USBUSB+ VSS 0 .1 m F
33W
*
0 .1 m F
*
VDD
10mF
100kW
PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE1
V33O
10kW 0 .1 m F
0 .1 m F
*
RES
0 .1 m F
47pF*
*
U S B D -/D A T A 47pF*
33W
* *
*
47pF 33W
VSS
U S B D + /C L K
HT82B40R
*
47pF
Note:
The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. Components with * are used for EMC issue.
Crystal or Ceramic Resonator for Multiple I/O Applications for HT82B40A
PA0~PA7 VDD USBUSB+ VSS VDD
10mF
100kW
0 .1 m F
PB0~PB7 PC0~PC7 PD0~PD7 PE0~PE1
V33O RES
0 .1 m F U S B D -/D A T A
0 .1 m F
VSS
U S B D + /C L K
HT82B40A
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Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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HT82B40R/HT82B40A
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
Rev. 1.10
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HT82B40R/HT82B40A
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
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HT82B40R/HT82B40A
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.10 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 39 September 4, 2009
HT82B40R/HT82B40A
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.10
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HT82B40R/HT82B40A
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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HT82B40R/HT82B40A
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev. 1.10
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HT82B40R/HT82B40A
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
Package Information
20-pin SSOP (150mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.335 0.049 3/4 0.004 0.015 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Max. 0.244 0.158 0.012 0.347 0.065 3/4 0.010 0.050 0.010 8
Symbol A B C C D E F G H a
Dimensions in mm Min. 5.79 3.81 0.20 8.51 1.24 3/4 0.10 0.38 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 4.01 0.30 8.81 1.65 3/4 0.25 1.27 0.25 8
Rev. 1.10
49
September 4, 2009
HT82B40R/HT82B40A
28-pin SSOP (150mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in inch Min. 0.228 0.150 0.008 0.386 0.054 3/4 0.004 0.022 0.007 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Max. 0.244 0.157 0.012 0.394 0.060 3/4 0.010 0.028 0.010 8
Symbol A B C C D E F G H a
Dimensions in mm Min. 5.79 3.81 0.20 9.80 1.37 3/4 0.10 0.56 0.18 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 6.20 3.99 0.30 10.01 1.52 3/4 0.25 0.71 0.25 8
Rev. 1.10
50
September 4, 2009
HT82B40R/HT82B40A
48-pin SSOP (300mil) Outline Dimensions
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in inch Min. 0.395 0.291 0.008 0.613 0.085 3/4 0.004 0.025 0.004 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.025 3/4 3/4 3/4 3/4 Max. 0.420 0.299 0.012 0.637 0.099 3/4 0.010 0.035 0.012 8
Symbol A B C C D E F G H a
Dimensions in mm Min. 10.03 7.39 0.20 15.57 2.16 3/4 0.10 0.64 0.10 0 Nom. 3/4 3/4 3/4 3/4 3/4 0.64 3/4 3/4 3/4 3/4 Max. 10.67 7.59 0.30 16.18 2.51 3/4 0.25 0.89 0.30 8
Rev. 1.10
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HT82B40R/HT82B40A
SAW Type 20-pin (5mm5mm) QFN Outline Dimensions
D
16
D2
20 1
b E e
15
E2
11 5 10 6
A1 A3 A
L
K
* MO-220
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.010 3/4 3/4 3/4 0.118 0.118 0.018 0.008 Nom. 3/4 3/4 0.008 3/4 0.197 0.197 0.026 3/4 3/4 3/4 3/4 Max. 0.031 0.002 3/4 0.014 3/4 3/4 3/4 0.126 0.126 0.026 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in mm Min. 0.70 0.00 3/4 0.25 3/4 3/4 3/4 3.00 3.00 0.45 0.20 Nom. 3/4 3/4 0.20 3/4 5.00 5.00 0.65 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.35 3/4 3/4 3/4 3.20 3.20 0.65 3/4
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
SAW Type 32-pin (5mm5mm) QFN Outline Dimensions
D 25 b E e A1 A3 L A 17 16 24
D2 32 1 E2 8 9 K
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in inch Min. 0.028 0.000 3/4 0.007 3/4 3/4 3/4 0.049 0.049 0.012 3/4 Nom. 3/4 3/4 0.008 3/4 0.197 0.197 0.020 3/4 3/4 3/4 3/4 Max. 0.031 0.002 3/4 0.012 3/4 3/4 3/4 0.128 0.128 0.020 3/4
Symbol A A1 A3 b D E e D2 E2 L K
Dimensions in mm Min. 0.70 0.00 3/4 0.18 3/4 3/4 3/4 1.25 1.25 0.30 3/4 Nom. 3/4 3/4 0.20 3/4 5.00 5.00 0.50 3/4 3/4 3/4 3/4 Max. 0.80 0.05 3/4 0.30 3/4 3/4 3/4 3.25 3.25 0.50 3/4
Rev. 1.10
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HT82B40R/HT82B40A
Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 20S (150mil), SSOP 28S (150mil) Symbol A B C D T1 T2 SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0+0.5/-0.2 2.00.5 32.2+0.3/-0.2 38.20.2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0+0.5/-0.2 2.00.5 16.8+0.3/-0.2 22.20.2
Rev. 1.10
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September 4, 2009
HT82B40R/HT82B40A
Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SSOP 20S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 16.0+0.3/-0.1 8.00.1 1.750.10 7.50.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.00.1 2.00.1 6.50.1 9.00.1 2.30.1 0.300.05 13.30.1
SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 16.00.3 8.00.1 1.750.1 7.50.1 1.55+0.10/-0.00 1.50+0.25/-0.00 4.00.1 2.00.1 6.50.1 10.30.1 2.10.1 0.300.05 13.30.1
Rev. 1.10
55
September 4, 2009
HT82B40R/HT82B40A
D
E F
P0
P1
t
W C
B0
D1
P K2 A0
K1
R e e l H o le ( C ir c le ) IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . R e e l H o le ( E llip s e )
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.10 14.20.1 2 Min. 1.50+0.25/-0.00 4.00.1 2.00.1 12.00.1 16.20.1 2.40.1 3.20.1 0.350.05 25.50.1
Rev. 1.10
56
September 4, 2009
HT82B40R/HT82B40A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
57
September 4, 2009

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